Phase-locked loop (PLL) and delay-locked loop (DLL) integrated circuits are frequently used to generate highly accurate internal clock signals on integrated circuit substrates (e.g., chips). These PLL and DLL integrated circuits may utilize phase comparators that compare a phase of a primary clock signal, such as a reference clock signal REF, to a secondary clock signal, such as a feedback clock signal FB. Phase comparators may generate output signals, such as a LOCK signal, which indicates whether the primary and secondary clock signals are in phase relative to each other (within some acceptable tolerance), and a COMP signal, which indicates whether the phase of the primary clock signal leads or lags the phase of the secondary clock signal when the two signals are not in phase relative to each other. If the COMP signal indicates a leading condition between the primary and secondary clock signals, then the PLL (or DLL) may operate to speed up the phase of the secondary clock signal. Alternatively, if the COMP signal indicates a lagging condition between the primary and secondary clock signals, then the PLL (or DLL) may operate to slow down the phase of the secondary clock signal. Conventional phase comparators may generate the LOCK signal by evaluating the presence or absence of a leading edge of the secondary clock signal within a time window centered about a leading edge of the primary clock signal. This time window is frequently referred to as a transition detection window. For high frequency applications, a relatively small transition detection window is required.
In particular, phase comparison operations may use an edge transition of one clock signal to capture a value (0 or 1) of another clock signal. For example, if a rising edge of a feedback clock signal FB captures a reference clock signal REF having a logic 1 value, then the COMP signal will cause FB to be advanced in time. Alternatively, if a rising edge of the feedback clock signal FB captures a reference clock signal REF having a logic 0 value, then the COMP signal will cause FB to be delayed in time. As will be understood by those of ordinary skill in the art, if the phases of FB and REF are different by an integer multiple of one-half the period (T) of the reference clock signal REF, then it will not matter whether the COMP signal indicates that the feedback clock signal FB should be slowed down or sped up to obtain a phase lock condition.
Operations to generate a LOCK signal within a phase comparator typically will work so long as the transition detection window is shorter than the period of the primary clock signal, and it typically does not matter whether the duty cycle of the primary clock signal is unity or not. However, operations to generate a COMP signal typically assume that the duty cycle of the primary clock signal is unity. When this is the case, the probabilities of capturing a logic 1 value or a logic 0 value are equivalent when comparing the relative phases of the primary and secondary clock signals. But, when the duty cycle of the primary clock signal is not unity, operations to generate a COMP signal and achieve phase lock between the primary and secondary clock signals may be inefficient. For example, if the duty cycle of the primary clock signal is 0.25 and a conventional linear search routine is used to achieve phase lock, then a worst case time shift of 80% of the period of the primary clock signal will need to be made to the secondary clock signal before phase lock is achieved. This is because a duty cycle of 0.25 corresponds to a primary clock signal that is high 20% of the time and low 80% of the time. Accordingly, if the secondary clock signal captures a logic 0 value of the primary clock signal immediately after a high-to-low transition of the primary clock signal, then the COMP signal will specify that the secondary clock signal needs to be slowed down to achieve phase lock. However, as the secondary clock signal is gradually slowed down, the secondary clock signal will repeatedly capture logic 0 values until time units providing a total of 80% of the period of the primary clock signal have been added to the phase of the secondary clock signal. A potentially better alternative in this case involves speeding up the secondary clock signal by only 20% of the period of the primary clock signal, but the conventional phase comparator has no way of knowing which shift direction (slower or faster) will achieve the faster lock condition. Furthermore, the relatively high degree of inefficiency in the phase locking operations may actually increase if a conventional binary search routine is used in place of the linear search routine.